ch precision logo

C1.2 Digital to Analog Controller

BROCHURE
ch precision logo

C1.2 Digital to Analog Controller

BROCHURE

Of course, it is digital conversion that lies at the heart of the C1.2. The perfect preservation of time and amplitude information is critical to reproducing musical signals stored in digital formats and we believe that the advances incorporated in the C1.2 build significantly on the solutions adopted in the C1, taking digital performance(s) to a whole new level.

Both noise and jitter are central to the design of any high-performance DAC. We have developed an entirely new MEMS-based, shunt regulated and thermally compensated clock for the C1.2, improving clock accuracy significantly (as well as providing highly developed clock-sync and external reference clock options). A four-fold increase in processing power has allowed us to further refine the proprietary CH-PEtER algorithms, introduce 32-bit fixed point processing and increase input compatibility to include all high-resolution digital formats, whether from optical or file replay sources. Our proprietary CH-Link HD interconnection allows the transfer of native DSD and MQA data in the digital domain, from the D1.5 transport to the C1.2. The AES/EBU and S/PDIF inputs accept PCM at up to 192kHz/24bit resolution, while the HD streaming input will accept PCM data at up to 768kHz/32 bit resolution and DSD512(8x). Local regulation of the DSP and FGPA further reduce the system noise floor. The DAC itself employs no fewer than four converter chips per channel, in a fully differential, dual-mono topology. The vital analog output stage is discrete, fully differential, Class-A and DC coupled. The modular input architecture ensures that the C1.2 remains future proof, able to adapt to changing digital standards or system demands.

ch precision - C1.2
ch precision - C1.2

Of course, it is digital conversion that lies at the heart of the C1.2. The perfect preservation of time and amplitude information is critical to reproducing musical signals stored in digital formats and we believe that the advances incorporated in the C1.2 build significantly on the solutions adopted in the C1, taking digital performance(s) to a whole new level.

Both noise and jitter are central to the design of any high-performance DAC. We have developed an entirely new MEMS-based, shunt regulated and thermally compensated clock for the C1.2, improving clock accuracy significantly (as well as providing highly developed clock-sync and external reference clock options). A four-fold increase in processing power has allowed us to further refine the proprietary CH-PEtER algorithms, introduce 32-bit fixed point processing and increase input compatibility to include all high-resolution digital formats, whether from optical or file replay sources. Our proprietary CH-Link HD interconnection allows the transfer of native DSD and MQA data in the digital domain, from the D1.5 transport to the C1.2. The AES/EBU and S/PDIF inputs accept PCM at up to 192kHz/24bit resolution, while the HD streaming input will accept PCM data at up to 768kHz/32 bit resolution and DSD512(8x). Local regulation of the DSP and FGPA further reduce the system noise floor. The DAC itself employs no fewer than four converter chips per channel, in a fully differential, dual-mono topology. The vital analog output stage is discrete, fully differential, Class-A and DC coupled. The modular input architecture ensures that the C1.2 remains future proof, able to adapt to changing digital standards or system demands.

Conversion type

  • Linearized R-2R, 4x PCM1704 per channel
  • 24 bit / 705.6kHz & 768kHz

DSP processing

  • CH-PEtER upsampler, synchronous, DSD to PCM conversion and resolution enhancer

Full scale analog outputs level

  • 5.1V RMS balanced
  • 2.55V RMS single-ended

Signal to Noise Ratio

  • > 120dB

Total Harmonic Distortion + Noise

  • < 0.001%, full scale, 22kHz BW

Weight

  • 20kg per unit

Dimensions

  • 440 x 440 x 133mm (W x D x H), 20kg per unit